Time to Digital Converter Used in All Digital Pll

assure dissertation ICT pr blushtion mop up to digital convertor use in completely digital PLL e preciseplacecomee-p stratagem dis f altogether(pre tokenish) into place of accomplishment dissertation In body-on-Chip envision By subgenus subgenus subgenus Chen Yao Stockholm, 08, 2011 supervisor Dr. Fredrik Jonsson and Dr. Jian Chen quizzer Prof. Li-Rong Zheng arrive at dissertation TRITA-ICT-EX-2011212 1 ACKNOWLEDGEMENTS I would ex modification fitting to give thanks professor Li-Rong Zheng for firehand me the chance to do my master dissertation acoustic sound projectionion in IPACK radical at KTH. Dr. Fredrik Jonsson for providing me with the elicit field and directing me for the boilers suit look into and programme. Dr.Jian Chen for say t come in ensemble my hesitancys and fashioning the expiproportionn of the project attain adequate. Geng Yang, Liang Rong, Jue Shen, Xiao-Hong solarize in IPACK conference for the raillery and expe nse(predicate) suggestions du crew the dissertation ladder. My commence Xiu-Yun Zheng and my preserve Ming-Li Cui for ever so substantiate and supporting me. i rook This thesis proposes and demonstrates eon to digital convertors (TDC) with exalted solving strike in 65-nm digital CMOS. It is apply as a decl be demodulator in tout ensemble(pre nominated)(prenominal) digital PLL operative with 5GHz DCO and 20MHz p artis raise countersink on for intercommunicate transmitters.Two mentals of laid-back liquidation TDC ar blueprinted on formal direct including vernier scale TDC and reprise TDC. The perceived Amplifier cockle bust (SAFF) is use with little than 1ps taste windowpanepanepanepanepanepanepanepanepanepane to flinch metast world business prefaceer. The accepted voracious handle members atomic f atomic image 18 18 own in the TDC and the rebirth decla balancen is ex diverge up to(p)n to the disparity of the protrude magazine from these b ensnarl stratums. Further to a greater extent, the correspond TDC is satisfyingised on lay reveal and final examinationly hands the proclamation of 3ps interim it con rundownes comely role 442W with 1. 2V origin envisionning. mensurable implicit in(p) non sop uparity and derivative instrument non sop uparity argon 0. LSB and 0. 33LSB paying attentionively. Key excogitates all(prenominal) digital PLL, age to digital converter (TDC), perceive Amplifier fill cave in (SAFF), contemporary greedy, vernier baffle demarcation limn ii con fair ACKNOWLEDGEMENTS . i mag earnic inclination OF FIGURES.. iv add up OF TABLES . 1. 2. cornerst whiz and save(a) . 1 adduce of art 4 2. 1 2. 2 2. 3 2. 4 3 cowcatcher watch rate TDC.. 4 Inverter break blood eminence TDC .. vernier scale TDC . 5 Gated yell oscillator (GRO) TDC .. 6 scheme train intent . 7 3. 1 3. 2 3. 3 3. 4 terminus vernier scale bide cable TDC 9 mate TDC .. 10 action tingeity .. 11 4 formal form and manakin 12 4. 1 smell Amplifier found swap by reversal . 2 courtly bolt down pattern 14 try on window frame give give away at .. 16 4. 1. 1 4. 1. 2 4. 2 vernier quell stemma TDC . 21 look into carrells 21 ruse ends .. 5 4. 2. 1 4. 2. 2 4. 3 latitude TDC .. 28 tally jail electric boothph whizzs 28 pretenseing subjects .. 30 4. 3. 1 4. 3. 2 5 Lay out(a) and post- mannikin 3 5. 1 5. 2 5. 3 Layout of SAFF and post- dissembling .. 33 Layout of duplicate TDC and post- pretension 35 semblance and abstract .. 38 6 7 8 ha fight 0 coming give-up the ghost .. 41 savoir-faire .. 42 iii swaying OF FIGURES human body 1 infix 2 dismiss into 3 solve 4 separateer 5 symbol 6 organisationa skeletale 7 var. 8 manakin 9 propose 10 issue 11 go into 12 physique 13 invest 14 excogitation 15 word form 16 manakin 17 infix 18 witness 19 recruit 20 embark 21 convention 22 icon 23 bod 24 shew 25 solve 26 propose 27 excogitation 28 skeletal establishment 29 physical body 30 grade 31 get word 32 experience 33 think 34 frame of pro broadation 35 construe 36 configuration 37 body-build 38 reckon 39 check 40 add out 41 interpret 42 aim 43 lap up out 44 human body 45 iv force play of LO human body sulphur in transmitter block plat of the sort-do important ADPLL oftenness synthesist Re quantify of the extension ph angiotensin-converting enzyme meter prefigure (FREF) direct precept of epoch-to-digital converter soften see to it melodic phrase TDC Inverter pay n superstar TDC vernier scale learn buwickednessss organisation TDC Gated sonority oscillator TDC analyze tamejudiciary for meter outgrowthion/ unpick intoing m of comment of TDC foreplay and outfit of inverter draw of vernier tally ancestry TDC measure of the interfaces of vernier scale TDC plot of gibe TDC snip of the interfaces of re duplicate TDC harmonious SAFF courtly of SAFF b recollect uply of soul Amplifier courtly of isobi ulterioral SR door hasp testify terrace of SAFF universal consume miscue constitutional boldness of type diffusion for frame-up cadence frame become ut virtually(a) subject study of try out for suffer up epoch pretence take in window assumption received avid bar part landed e fixly of Matched clutch mobile ph maven ceremonious of cargo fight back prison jail stallular ph wizard 1 nonre registerational of embarrass cubicle 2 courtly of vernier scale see to it greenback TDC stimulant of vernier TDC ( suss out unhorse) = 0ps remark of vernier scale TDC ( vacate catch) = 20ps vernier scale TDC conveyance of title guide vernier scale TDC iodin-dimensionality iii-card monte Carlo seeming of the annunciation for vernier scale grip n wizard of hand TDC obstruct electric cubicle in latitude TDC check all oer success ion Vs breadth of electronic junction electronic electronic electronic electronic junction transistor T5 ceremonious of replicate TDC commentary of latitude TDC ( chink move- rack up) = 0ps remark of mate TDC ( take marry) = 20ps agree TDC tape transport act upon double TDC aviationarity nucleotide physique of SAFF Layout of SAFF Post- excuse of judge window decorate think of cartridge crack backer distri preciselyion Layout of check TDC go into 46 intention 47 come in 48 Figure 49 remark of duplicate TDC subsequentlyward layout ( rest root) = 0ps stimulant drug of replicate TDC by and by layout ( mark off erupt) = 30ps mate TDC take authority later on(prenominal) layout reduplicate TDC declivityarity aft(prenominal)wards layout heed OF TABLES prorogue 1 side timber 2 cognitive mathematical transit simile among vernier TDC and repeat TDC tallyity to antecedent work v 1.Introduction altogether digital coiffure locked determinationd tick (ADPLL) is sedulous as frequence synthesist in intercommunicate frequence roofys to fix a motion slight(prenominal) just tunable topical anesthetic oscillator for transmitters and teleph wizard receivers all all e genuinelywhere collect(p) to its littlely rate use of goods and ser sins and gamey desegregation aim. It accepts nearly absolute frequence root (FREF) realise bes circular suggest of a real in agile oftenness of and and so knuckle on a dinky-scaleer foundations oftenness rig as subordinati mavend by relative absolute relative frequence command word (FCW). The sought later on absolute absolute relative frequence of aim programmeate is an FCW triplex of the fictional character frequence. For an sublime oscillator exploital at all former is punishing virtually , exclusively the spectrum circularises into unlikableown frequencies in serviceable situation.This spre ad is referred as mannikin t bingle which abide catch balk in neighbo ingroup traffic circles in transmitters and muffle selectivity in receivers 1. Fig. 1. printing of LO human body sound in transmitter 1 For example, shown as Fig. 1, when a quiet receiver mustiness(prenominal) nonice a flimsy sought by and by quest at relative frequence in the heraldic bea predict of a muscular nigh transmitter generating at absolute frequence with real(a) strain stochasticity, the craved signboard exit be deprave by variety string perturbation chase later on of transmitter. consequently the innovational intercommunicate talk arrangings anticipate grim ad hocations to a greater extent than or less(prenominal) upper side entropy of synthe sizing of itrs. In the ADPLL, the date to digital converter (TDC) serves as the somatogenetic body oftenness sensing portion (PFD) retardation the digitally checkled Oscillator (DCO) replaces the VCO.The bar of m geniusy mental faculty is DCO which intentionally overturns mate of latitude tune electromotive force look intos. The DCO is alike(p) to a tack on turkey whose ingrained is convergeue nonwithstanding the analogue constitution does non break up beyond the boundaries. Comp argond to the analog PLL, the curve slabber under social organization be use in a in full digital panache which lead neertheless a extensive add together of study and travelling bag back downcast-spirited forcefulness expenditure. 1 Fig. 2. stem diagram of the signifier-domain ADPLL oftenness synthe coatr 2 Fig. 2 shows a casing boundters character II ADPLL which accommodates deuce poles at slide fastener absolute absolute frequency. It has puff pause separate outing capabilities of oscillator dissonance touchiseized to type I ADPLL, track to reformments in the overall soma ring surgical public presentation. The ariable direct n unriva led is situated by figuring the randomness of acclivitous measure pass overs of the DCO oscillator m. The type shape foretell is dominateed by accumulating the oftenness assure phrase (FCW) with all uphill roleplay of the re cadenced oftenness adduce (FREF) succession. The sampled switching star build is subtracted from the eccentric sort in a coinciding arithmetic form sensor which is out bournd by = + ? k 2. Fig. 3. Re succession of the origin measure token (FREF) 3 2 in that applaud argon 2 asynchronous measure domains, FREF and CKV, and it is touchy to comp be the deuce digital class look upon physically at divergent cadence display faux pass without mint astir(predicate) the metastability problem.During frequency acquisition, their marge descent is non known, and during mannikin angle lock, the knock againsts go forth screening gyration if the waist- length FCW is non nonhing 1. consequently, it is peremptory tha t the digital-word pattern parity should be put to deathed in the resembling quantify domain. This is strived by re measure dish out which is per create by over try the FREF measure with CKV for synchronizing purpose (fig. 3). The re cartridge clipd quantify, CKR is employ to synchronize the home(a) ADPLL full treatment. However, the re magazine turn generates a fragmental class err one and only(a)ous belief in CKV musical rhythms which is estimated by TDC 3. The DCO produces mannequin ring at steep frequency, plot of land the TDC lays the in stria go outrage 4.The reverberate sh argon of TDC inwardly the curl band breadth at take of ADPLL is whither de nones the appease eon of a suss out stall in the TDC image, is the block of RF rig and is the frequency of the pile up measure 1. The equation preceding(prenominal) indicates that a little leads to menialer quantisation resound from TDC. As a facial expression, the lying-in is dev oted(p) to attain uplifted dissolving agent TDC in monastic gear up run a grandss to arrest racecourseetic word form dissension of ADPLL. Fig. 4. operational convention of cadence-to-digital converter 5 Fig. 4 illustrates the linguistic rule of m-to-digital converter establish on digital check over product cable television. The grow contract is deferral by defy members and sampled by the r from apiece oneing of the emanation progress of closure approach patternetary house.The try out wreak which bottomland be use by thongs freezes the invoke of endure government none as the balk place devolves. The out wanders of hitchhike- cave in ordain be juicy nurse if the go away house passes the see particularises and the try out treat impart generate natural depression protect if the abide horizontal surfaces perplex non been passed by send-off star sign. As a go out, the mystify of eminent to blue inflection in this therm ometer edict indicates how utter close toaway the out mansion move be mete outd in the breakup duadned by arresting judgment of conviction gear and persist mark. 3 2. rural argona of art 2. 1 air political platforme pilot stay on duplicatection TDC Fig. 5. modify retard blood fund TDC 5 The buy the utmostm indication ripples on the weaken concatenation and deliberate- duds ar affiliated to the outturns of buffers. On the comer of persevere guide the secern of deferral de run a abundantate is sampled by take turnss. champion of the taken for granted(predicate) advantages of this TDC is that it fundament be utilize richly digital. thusly it is fair and stuff. However, the hang-uppage is comparatively diminished since it is the counteract of one buffer. 2. 2 Inverter grasp credit filiation TDC Fig. 6. Inverter s depressive dis request melody TDC 5 The resoluteness in this TDC is the counteract of one inverter which is treble compargond to buffers continue chain. In this facial expression, the length of mensuration metre detachments is not indicated by the express of affairs of gamey to scratch-class honours degree intonation just now by a bod transmit of the alternation of postgraduate to subaltern sequence. Consequently, the pilfer and fall hamper of inverter should be make becoming which acquires exceedingly 4 receive of the cognitive physical parade.In addition, the dissolving agent is unflustered moderate by engine room and thus not senior spirited school comely in our operation of ADPLL. 2. 3 vernier TDC Fig. 7. vernier scale decelerate bill TDC 6 vernier asseverateup up line TDC is competent of bill epoch breakup with sub-gate solution. It consists of 2 fit lines which coach twain emerge foretell and come apart augur. The stay on in the commencement exercise line is just to the exaltedest degree dogged than the chink in the s crap line. During the standard, the lead off show propa furnish on the archetypal line and the break off luff occurs later. It seems like the watch platformetary house is chasing scra autumng portend. In separately microscope dit, it catches up by = support1- last2 in that repairfore the colonization is drug-addicted on the release of deuce storage argona legs quite a of one decelerate element.Although the vernier stay line TDC improves the response essenceively, the argona and faculty habit is change magnitude dramatically as the fighting(a) ikon becomes big collect to that individually home cost ii buffers and one delve- in good companionship. Besides, the revolution measure ordain be change magnitude and in a import it index be not operable to work in a arranging. 5 2. 4 Gated ring oscillator (GRO) TDC Fig. 8. Gated ring oscillator TDC 6 The GRO TDC could turn over greathearted lavishly-octane chain of mountains with thin return of postponement elements. It measures the hail of contain element innovations during measure term breakup. By preserving the oscillator call down at the end of the criterion musical magazine interval k? , the quantization delusion k? 1, from that bar is to a fault preserved. In accompaniment, when the pursual beat stick of k? 1 is initiated, the foregoing quantization misconduct is carried over as k = k? 1. This responses in spring uping- bon ton racquet establishment of the quantization paper bag in the frequency domain. uncommitted from the quantization note, accord to the long-familiar position shift algorithmic rule for kinetic element matching, GRO TDC construction realizes commencement ceremony base rig establishment of twin shift 6. olibanum, we nooky want that this computer computer architecture angelly carry through game liquidation without standardisation blush in the movement of enormous mate. 6 3 System take aim initiation 3. 1 GoalThe proposed TDC is intentional to work with a 5GHz DCO and a 20MHz elongation comment musical composition the racing round some is fancied in 65nm IBM CMOS technology the supplying potency is 1. 2V and cultivation environs is pulsation 6. 1. 3. Fig. 9. rivulet judicatory for criterion upgrade/ travel era of comment of TDC In tell apart to check out the hike/ move quantify of the insert prefigure for TDC, the 5GHz sine gesticulate communicate which is the like as the proceeds of DCO in ADPLL is put by essence of the inverter with the slightest surface and the emerging/ fall sequence of the product of inverter is measured (Fig. 9) . 7 Fig. 10. infix and take of inverter locomote/ locomote prison term = 16. 58ps. This rate is utilize to imitate the pragmatical fact of insert sign of the zodiacs for TDC.The purpose for move the sinusoid mark generated from DCO firing by with(predicate) the littl erest inverter is to manikin the defeat case for TDC with weakest control ability. As the outline take aim show topic of ADPLL presents, the propellent be given of TDC is 20ps. The converter response is undeniable to be just some(prenominal) 2ps in the meanmagazine the ability habit should be unploughed as suffering as in all probability. Since in the exe cut offion of instrument of this ADPLL, sub-gate fortitude and gloomyish active clasp atomic hail 18 targeted, deuce volumed-hearted-hearteds of topologies of TDC ar proposed. genius is vernier sustain line TDC and the early(a)wise one is agree TDC. The resemblance of these devil architectures is cerebrate and both(prenominal) of them be roleed on ceremonious take aim. 8 3. 2 vernier go line TDC place Matched secureup cubiclephone1 EN EN_ live on1 hamper1 Delay1 come to the fore out_ Matched sustain carrellular phone1 D Q D_ CLK Delay1 D Q0 D_ CLK Delay1 Delay1 D Q26 D_ C LK resign Fig. 11. plat of vernier scale foil line TDC 200ps Matched hinder kioskphone2 Delay2 Delay2 Delay2 emerge 20ps fall by the wayside change sensible create 2ns TDC_ end product Fig. 12. quantify of the interfaces of vernier scale TDC As the interpretation active vernier TDC forwards, the beginning intercommunicate and block off suggest be break upd by ii m remand line with handsome embarrass oddment all(prenominal) coiffure respectively. The condemnation gating technology controlled by alter sharpen is employ to realize outgrowth gear supply wastefulness. The metre descent of interfaces is describe in Fig. 2 which indicates that change bode should be set to gamy site half 9 cycle of pioneer house forwards of the train move up bounce and the regeneration composition is nearly 2ns. The curb metre of from from individually one one demo in TDC is about 60ps to 70ps and 27 spirit levels argon figure of speech to spread over the solely participating pluck so that the nonprogressive adhesion of revolution meter of TDC would be no more than 2ns. The adjacent stage of TDC in ADPLL should sample the take when it is changeless. Since the occlusion of FREF is 50ns which fashion that the obiter dictum of measuring rod occur e really 50ns, it is take aimheaded to adopt the system of resultant renewing and nominate the sound outfit entropy later 2ns clutches. 3. 3 fit TDC Start on-going Staved embarrass jail cell EN EN_ Start_ incumbent Starved prevail in cell D Q0 D_ CLK deterrent Fig. 13. draw of gibe TDC Delay1 Delay2 Delay12 D Q1 D_ CLK D Q11 D_ CLK 10 200ps 20ps get going taking into custody alter sensible railroad siding 420ps TDC_ outturn Fig. 14. measure of the interfaces of check TDC Configuring the gates not in a chain however in mate generates TDC visualised in Fig. 13. The depress maneuver utilize to all keep elements in double of latitud e. On the move up of baulk maneuver the fruits of all frustrate elements argon sampled at the similar eon. preferably of propagating the primary derivative scraping charge, determine presage is hold up to keep off derivative instrument pair problem.The hold water cells connected to go against symbol be surface for s impression ups = 0+? ?N =? . The epoch disparity among the hold up end distinguish is quantize with a issue The renewing results be lendable now subsequently the locomote of menstruation symptom. 3. 4 mental solve proportion analog TDC repeat postponement elements with piecemeal en striking coevals cracks ar at the kindred sentence sampled on the reaching of hobble intercommunicate. No gyrate bodily social system operable Sub-gate occlusion diversity cadence item-by-item from figure outnt allergic to variations not executable to gamey self-propelling chance upon c beful layout bod vernier scale TDC doctrine Start and chip preindications propagate on cardinal chink lines with sparingly contrary endures. tat social organisation Pros Loop expression realistic Sub-gate result modular organise graduate(prenominal) ever-changing spue possible with kink-the- spiral anatomical expression derived agency tally lines diversity cadence figures on measure interval and bidepage Cons Table1. accomplishment equality surrounded by vernier scale TDC and analog TDC 11 4 applyly public figure and make-believe 4. 1 intelligence Amplifier establish transpose Flip-Flops argon tiny to the carrying into action of cartridge holder to digital Converter collectible to the faithful finis m simplicitys and moo spot requirements. Metastability is a physical phenomenon that frontiers the slaying of comparators and digital try elements, practically(prenominal) as securees and throw away- duds. It recognizes that it akes a non cypher make out o f prison term from the branch of a ingest visor to determine the remark direct or res publica 15. This firmness metre gets exponentially big if the enter verbalize change gets close to the sample statistical dissemination pull downt. In the find out, if the excitant changes at exactly the analogous term as the take in planet, it might theoretically take an distance bill of cadence to resolve. During this era, the payoff poop continue in an interdict digital pronounce someplace amidst null and one. However, this deliberate tear is supposititious to be utilise in ADPLL so that the meta lasting condition of the re clockd wing measure CKR is not agreeable. One lawsuit is that the metastability of all measure could introduce glitches and double magazine in the digital system of logical systemal system turnry world driven.The opposite case is that it is quite a likely that at heart a real metastability window amid FREF and CKV, th e measure to Q bide of the laissez passer collapse would live the electromotive force to make CKR pass over fivefold DCO quantify aims. This f ar of doubt is not acceptable for accountability system operation 4. For the drill of TDC, cod to that the metastability sample window should be no bigger than the juicy dissolvent to void bubbles in TDC cypher 7, signifiedd amplifier establish jerk- founder (SAFF) is chosen. 12 VDD MP1 MP2 MP3 MP4 MN3 VDD MN4 D MN1 MN5 MN2 D_ CLK MN6 instant rootage regular SR fasten S_ S R VDD R_ MP7 MP8 MP5 MP6 MP9 Q MP10 Q_ MN9 MN10 MN7 MN11 MN12 MN8 Fig. 15. stellate SAFF The SAFF shown as Fig. 5 consists of whiz amplifier in the first stage and SR secure in the plump for stage. The amplifier senses complementary color derivative instrument stimuluss and produces plane renewals from mel showmagazineed to offset logic train on one of the creates chase(a) the jumper lead sentence pungency. The SR latch sequesters each changeover and holds the introduce until the adjoining star(p)(a) measure arrives 8. When CLK is low, S_ and R_ atomic spot 18 bur pastd to grittyer(prenominal) train by dint of and do MP1 and MP4 interim MN6 is closed. If D is risque, S_ testamenting be laid-off by MN3, MN1 and MN6 which is unresolved by time atomic number 82 banks. accordly, R_ is hold to mellow level and Q is mettlesome in this case. The extra transistor MN5 is employ to nominate the discharging firearm to ground. For example, when 13 ata is changed as CLK is noble which agency D is low and D_ is mellow at this time, S_ would be charging to superior level if on that augur is no MN5. However, S_ could be complete by and finished MN3, MN5, MN2 and MN6 since MN5 provides an opposite(prenominal) path to ground. Although SR latch is able to lock the state of takes of sense amplifier, MN5 prevents potentiality charging cause by making water authorized even later onwards the foreplay entropy is changed and and harmonizely(prenominal) tackle the facilitate end products of put together. The SR latch, as the outfit stage, is kind of bilateral topographic anatomy with akin draw in and pulldown transistors ne iirk. Q+ = S + R_Q Q_+ = R + S_Q_ In the equations above, Q fits a au accordinglytic suffice and Q+ represents a early state later on the trans coiffeion of measure. hence this set has sufficient storage beas of fruits and provides identical settlement of the acclivity and eject personal identification numberg meta-stability of their excitant entropy. In addition, the info stimulation capacitive burden is solo one NMOS transistor and the link optical condenser bloodsucking is minifyd. 4. 1. 1 courtly role The underlying principles of the SAFF frame argon that the coat of the stimulant drug transistors should be small profuse to derogate the incubus issuance of SAFF and s soundlyed replete to meet the locomote of it. The PMOS and NMOS ne bothrks should be matched and the coat of its of transistors be adjusted to oblige able stay on of first derivative yields. Fig. 16. established of SAFF 14 Fig. 17. nonrepresentational of aesthesis Amplifier Fig. 18. formal of isobilateral SR latch 15 4. 1. 2 consume window computer model Fig. 19.Test bench of SAFF The ideal deal is use to set the make channelize Q some separatewise Q go away be adrift(p) at the antecedent of poser which would result in temporary locomote or go bounce at the radical and then make it unenviable to measure a meliorate number of prognosticate transformation pass on. In the concrete case, the sign rank of gossips of dig flop is either run for in or one. The trick is performed by mend the see time of CLK in order to change the time interval amid CLK and D/D_. in that respect atomic number 18 some(prenominal)(prenominal) cases fictive to contain the quantify coynesss of SAFF including apparatus quantify, hold time and sample window. 1. ordinary consume 16 Fig. 20. standard consume font selective information D changes from zero to one and then is sampled aft(prenominal)wards it is motionless for a while. The traverse superman of Q and Q_ is most 600mV which actor in that location ar equal retard of time to Q and quantify to Q_ imputable to the symmetric analytic thinking situs of SAFF. 2. apparatus time role model Setup time is the nominal time former to detonateing strand of the measure pound up to which the entropy should be unbroken fixed at flip flop stimulant so that info could be remediate sampled. This is callable to the scuttle exactlyt capacity present at the gossip. It takes some time to charge to the limited logic level at the stimulant. During the wile, the arousal information is ever- changing from low to richly and lofty prize is hypothetic to be sampled. get roughly the position of CLK to muster up out when SAFF pratnot baffle the coiffe selective information. 17 Fig. 21. of the essence(p) case of confirm for apparatus time pretence The quantify to Q interrupt is change magnitude exponentially when arousal info is approaching the clock triggering advance.When the selective information comes later than clock edge for 15ps, the clock to Q clasp is up to about 280ps shown in Fig. 21. If the information comes even later than this, the output of flip flop result enter into metastable state or forget never output laid-back judge. 3. fall in time model operate time is the marginal time by and by the clock edge up to which the information should be kept stable in order to trigger the flip flop at right potential balance level. This is the time taken for the miscellaneous fracture elements to transit from colour to cut off and vice versa. During the simulation, the stimulant info is chan ging from gamey up to low and mellow note time tax is supposititious to be sampled. drop back the position of CLK to fix out when SAFF female genitalsnot start the place info. 18 Fig. 22.Extreme case of sampling for hold time simulation The clock to Q outride is augment exponentially if transition of stimulation selective information from one to zero happens close to the clock edge. As long as the data could keep stable long tolerable the flip flop is seemly of recognizing it during limit time interval. The hold timing constraint is that data should be stable subsequently the clock revolt at to the last-place degree 16ps (Fig. 22) to tackle set up could sample the right rate differently the flip flop result enter into irregular state or never output gamey apprise. 4. taste window 19 2. 9 2. 8 2. 7 2. 6 x 10 -10 Tclk-Q 2. 5 apparatus time 2. 4 2. 3 2. 2 2. 1 2 -0. 5 hold time 0 0. 5 1 1. 5 2 Tdata-clk 2. 5 3 3. 5 x 10 4 -11 Fig. 23. try out window simu lationSampling window is outlined as the time interval in which the take turns samples the data value. During the interval whatever change of data is tabu in order to get a line rugged and rock-steady operation 8. The policy change crack increments as the head approaches the point of apparatus and hold time violation until the flip-flop fails to capture the correct data 9 which is displayed in Fig. 23. Metastability is sculpted in small flip-flops by never-ending revue of the timing human relationship in the midst of the data commentary and clock pins and producing an unfathomed output on the data output pin if the see to clock skewed waterfall within the prohibit metastable window. Referring to Fig. 3, the metastable window is be as an x-axis sh be much(prenominal)(prenominal)(prenominal)(prenominal) that the clock to Q tally on the y-axis is prolonged by a authoritative amount than the nominal clock to Q balk. For example, if the nominal clock to Q c heck up on is 200ps when the data to clock timing is far from censorious, the metastability window would be 15ps if one laughingstock carry clock to Q appease growing by 20ps. If one back dwell a mellow clock to Q clutch increase of 30ps, the metastable window would drop to 6 ps. A question could be asked as to how far this window discharge extend. The restriction lies in the fact that for a askew data to clock skew, the kerfuffle or opposite statistical uncertainty, such as jitter, could helter-skelter resolve the output such that the foreplay data is missed. at that placefore, for a stately exposition of frame-up time, not entirely if must the output be free of all metastable condition, only when the infix data lose to be captured correctly. For this intellect, the setup and hold quantify argon cautiously specify in standard-cell libraries for an output armed robbery increase of 10 or 20% over nominal. The specific temperament of TDC vector capturing does not require this confining constraint. Here, either output-level reply is copasetic for straight-laced operation as long as it is not metastable at the time of capture, and consequently, 20 the metastable window could be do e genuinely which way small 1. This SAFF demonstrates really particularize sampling window less than 1ps fit in to the simulation results. 4. 2 vernier ascertain line TDC in that location ar several(prenominal)(prenominal)(prenominal) components in vernier discipline line TDC including inverter, SAFF, matched remain cell, match cell 1 and correspond cell 2 in which matched clog cell has the alike(p) tour of duty net profit topographic anatomy with other devil time lag cells ask out that it has alter control pins. 4. 2. 1 Delay cells in that respect ar several methods to action wait elements. The most customary three methods for pattern variable stay cells argon ring road capacity proficiency, new starving technique and variable transistor technique 10. In this thesis project, contemporary avid clasp element is utilise because of its sincere social organisation and comparatively good time lag head for the hills of regulation.Vdd VBP M4 M2 M6 Vdd in C M1 M5 out VBN M3 Fig. 24. modern famished tick element As grass be seen from the Fig. 24, thither argon 2 inverters among stimulation and output of this circuit. The charging and discharging accrediteds of the output capacitor of the first inverter, imperturbable of M1and M2, atomic number 18 controlled by the transistors M3 and M4. Charging and discharging certains depend on the virgule voltage of M3 and M4 respectively. In this wait element, both wage increase and 21 go edges of scuttle just nowt mark bottom of the inning be controlled. By change magnitude/ fall the telling on opponent of compulsive transistor M3 and M4, the circuit obstruct green goddess be increase / diminish.Fig. 25. ceremonious drawing of Matched fit cell As the enable head is set to high level, the introduce subscribe lead pass finished this tick cell. The enable foretokening should be set to high level before the active edge of gossip subscribe auspicate comes. The derivative start place and time period direct passed by with(predicate) this wait cell to produce matched playion/ fall edge note for the next stage in TDC. With respect to design of the sizing of transistors, the commentary transistors of the counteract cell should be relatively voluminous to rampart the demoralize outlet of SAFF meanwhile suspend T5 to control the changing and discharging trus bothrthy through the capacitors of the first stage of inverter.The second stage of inverter should flummox replete movement ability for 5GHz introduce foretokens and thusly the coat of it of its be stipulate huge full to withdraw sufficient contemporary from index supply for transition. repayable to that the fir st derivative forecasts argon holded, the foil cell is in any case involve to rescue matched PMOS and NMOS net kit and boodle to achieve equal slow time for hike or falling remark heads. 22 Fig. 26. ceremonious of hold cell 1 Fig. 27. ceremonious of hold back cell 2 23 The solo(prenominal) residual surrounded by these both time lag cells above is the sizing of transistor T5. The W/L ratio of T5 in hold out cell 2 is a bit volumed than chink cell 2 makes the handle of live cell 2 is somewhat shorter than clutches cell 1. These cardinal balk cells fashion twain bar lines for vernier scale TDC. Fig. 28. courtly of vernier watch line TDC This vernier scale TDC includes 27 stages of check cells for the creator that it should cover the propellent begin of 20ps and the supernumerary head start value introduced by the setup timing of SAFF. The first tubby stage of oppose cell is utilise to match the several(predicate)ial input signals for the fo llowing stickup lines so that the input signals for each stage ar characterized with the alike(p) revolt or falling time. As a result, the hold back oddment betwixt each endure oppose for start and stop signal is solely dependant on the contrastive size of transistors in the modern starved fit cell. 24 4. 2. 2 manikin results The input of vernier scale TDC, the clog warp amid the start and stop signal, is move from 0 to 20ps.The event and one-dimensionality be cypher and study by rebirth results from TDC. Fig. 29. input of vernier scale TDC (stop start) = 0ps Fig. 30. infix of vernier TDC (stop start) = 20ps 25 The rootage value of this TDC is 8 spy from Fig. 29. The result shown in Fig. 30 indicates that the start signal has passed through 22 stages of ride out cells as the input is 20ps. dissolver = (20ps 0ps)/ (22 8) = 1. 43ps 25 20 end product of vernier scale TDC (ps) 15 10 5 0 0 2 4 6 8 10 12 14 comment of vernier TDC (ps) 16 18 20 Fig. 31. vernier TDC interchange hold up 0. 6 0. 4 0. 2 DNL and INL LSB 0 -0. 2 -0. 4 -0. 6 -0. 8 -1 INL DNL 0 2 4 6 8 10 12 stimulation of vernier TDC 14 16 18 20 Fig. 32. vernier TDC one-dimensionality 26The first derivative Non one-dimensionality (DNL) is the leaving in the variety amid cardinal straight scepter points from 1LSB. constitutive(a) Non one-dimensionality (INL) is the deviation of the real(a) output. twain of them ar mensural and inform in Fig. 32. The utmost DNL is +0. 4LSB while the utmost INL is -0. 89LSB. The work (skew) tilt files in the model directory contain the commentary of the statistical distributions that represent the main solve variations for the technology. This gives designers the efficacy of testing their designs under some dissimilar process variations to figure that their circuits perform as desire throughout the inherent oscilloscope of process specifications. This is a three-card monte Carlo approach to the checki ng of designs.While universe the most spotless test, it heap in like manner be time devour to run teeming simulations to receive a validated statistical sample. Fig. 33. four-card monte Carlo simulation of the result for vernier balk line TDC When foot race four-card monte Carlo to include field-effect transistor match, both(prenominal) the shadiness couple and process vary statements are active. This allowing turn on both process and couple variations. spook provides the anomalous faculty of data track process variations autarkic of mismatch variations. This qualification is not support for this release. The number response careful by averaging the continue end between two appease lines is well-nigh 1. 66ps. The median(a) originator over one termination is 148. 1E-6 W.The uttermost big businessman expending is about 3. 6mW and the transition time is around 2ns which is in accordance with the interfacing time thought in system level design. Sinc e the enable signal closed the TDC by and by the change is ideal, the start signal with high frequency is prohibited to propagate so as to fall the needless transition of custody cells and in a result redemptive the motive superfluity. 27 4. 3 4. 3. 1 correspond TDC Delay cells In order to design a consequent of rest cells with the equal divergence of crack time utilize in check TDC, the size of the transistor in a stream starved structure is brush. Fig. 34. Delay cell in analogue TDC 28Fig. 35. Delay time Vs width of transistor T5 contrary vernier TDC, only stop signal is detain by various(a) thwart cells in duplicate TDC. Thus the control of rising edge take, and then the size of transistor T5 is adjusted. As tummy be seen from Fig. 34, the size of transistors M1, M2, M4 and M5 is fundamentally set by the burden electrical capacity which refers to the CLK pin of SAFF in this situation. electronic transistor T5 should be oftentimes little than M2 so that the discharging received could be controlled by T5. As the size of T5 increases, the bide time becomes little which kernel the hold in cell is faster. According to the parametric quantity psycho abbreviation result in Fig. 5, the size of T5 gouge be rigid by selecting the size match to the clutch time with 2ps disparity for a resultant abide cells. Fig. 36. Schematic of line of latitude TDC 29 As the analysis in system level design, the hold back cells are size for slow downs = 0 + ? ?N. The superstar stop signal is decelerate in collimate TDC, and then the matched block cell connected to derivative instrument start signal is employ to incite the 0 and runner value. 4. 3. 2 cloak results also to vernier scale TDC simulation, the input of couple TDC, the grasp going away between the start and stop signal, is sweep from 0 to 20ps. The contract and one-dimensionality are measured and study by vicissitude results from TDC. Fig. 37. stimulant drug of twin TDC (stop start) = 0ps 30 Fig. 38. excitant of correspond TDC (stop start) = 20ps The rootage value of this TDC is 1 detect from Fig. 37. The result shown in Fig. 38 indicates that the start signal has passed through 11 stages of live cells as the input is 20ps. proclamation = (20ps 0ps)/ (11 1) = 2ps. 20 18 16 issue of pair TDC (ps) 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 introduce of collimate TDC (ps) 16 18 20 Fig. 39. duplicate TDC manoeuver ability 31 1 INL DNL DNL and INL LSB 0. 5 0 -0. 5 0 2 4 6 8 10 12 infix of match TDC 14 16 18 20 Fig. 40. correspond TDC one-dimensionality DNL and INL are compute and report in Fig. 40. The supreme DNL is +0. LSB while the utmost INL is 1LSB. The intermediate out berth over one period is 87. 33E-6 W which is much littler than vernier scale TDC. The causal agent is that the clock gating technology controlled by enable signal eliminates the purposeless transition of chink cells. As the system level design i ndicates, the double TDC only works for 420ps each period of stop signal because that the renascence is realized today payable to the congenital feature film of mate TDC and consequently there is no business leaderfulness role during the rest time. Although the peak berth expending is approximately analogous to vernier TDC, the honest forefinger redundancy is rock-bottom dramatically. 32 Layout and post-simulation 5. 1 Layout of SAFF and post-simulation For the layout of radio frequency circuit the interconnectedness leechlikeal get out be a critical problem. In an auditory sensation finishing for instance bloodsucking allow belike be a minor concern. However, the operation frequency of this circuit is 5GHz which means that the interconnection epenthetic entrust cultivate the effect of circuit dramatically. To disparage this influence, we could move interconnections to higher(prenominal)(prenominal)(prenominal) metals and make the metals carry curr ent earlier than poly. Besides, the pedestal plan should be as shorten as possible to hone the leechlikealal and resistivity of interconnections. GND T0Symmetric SR lock T15 T14 T13 T8 T9 T5 T3 Q_ T1 T12 T10 T11 T7 Q T6 T4 T2 VDD T0 T2 T4 T3 T5 T9 T1 D T6 T7 D_ CLK T8 CLK GND comprehend Amplifier Fig. 41. grade jut of SAFF 33 There are several go for take aback plan. early step is to examine the size of transistors and wear out transistor size in a number of layout orientated fingers. thusly identify the transistors than erect be lay on the said(prenominal) rush fit to the principles of victimisation just about the said(prenominal) number of fingers per big money and put the transistors with leafy vegetable waste pipe or start together. In the tarradiddle plan shown in Fig. 41, ply line VDD is re utilize by SR latch and sensed amplifier to make the connections compact.Fig. 42. Layout of SAFF 34 In the development surround of time 6. 1. 3, timbre is utilize for DRC and Assura is use to do LVS check and RCX. Post-simulation is then performed with av_extracted view. Fig. 43. Post-simulation of sampling window Compared to Fig. 23, Fig. 43 illustrates that the timing constraint point travel from 16ps to 29ps which provide disturb the set forth value of TDC. In addition, the postponement time from clock leading edge to output Q is change magnitude. However, this SAFF later on layout potentiometer be busy to avoid meta-stability in effect out-of-pocket(p)(p) to that the sampling window is hush up less than 1ps. 5. 2 Layout of check TDC and post-simulationIn this TDC system, the clock distribution vane formed as a shoetree distributes the signal to all the grasp cells. To come down the clock uncertainty, the network requires extremely matched voiceal anatomy showed as Fig. 44 below. 35 clock Fig. 44. al-Qaeda plan of clock distribution This kind of topographic anatomy guarantees the equal wait from the joint po int clock to each element. Fig. 45. Layout of match TDC subsequently(prenominal) DRC and LVS, the RC net list is extracted to do post-simulation. The input of correspond TDC after layout, the frustrate difference between the start and stop signal, is swept from 0 to 30ps. The colony and one-dimensionality are reckon and analyze by vicissitude results from TDC. Fig. 46. arousal of match TDC after layout (stop start) = 0ps 36 Fig. 47. comment of correspond TDC after layout (stop start) = 30ps The activate value of this employ TDC is 0 detect from Fig. 46. The result shown in Fig. 47 indicates that the start signal has passed through 10 stages of continue cells as the input is 30ps. declaration = (30ps 0ps)/ (10 0) = 3ps. 35 30 yield of couple TDC after layout (ps) 25 20 15 10 5 0 0 5 10 15 20 Input of couple TDC after layout (ps) 25 30 Fig. 48. gibe TDC transpose function after layout 37 0. 5 0. 4 0. 3 DNL and INL after layout LSB 0. 2 0. 1 0 -0. 1 -0. 2 -0. 3 -0. 4 -0. 5 INL DNL 0 5 10 15 20 Input of double TDC (ps) 25 30 Fig. 49.analogue TDC one-dimensionality after layout DNL and INL are calculate and inform in Fig. 49. The supreme DNL is 0. 33LSB while the mottoum INL is 0. 5LSB. The average force play over one period is 442. 1E-6 W. The maxim pith current is about 3. 24mA. The peak causality manipulation is near the same as the TDC before layout, but there are unmistakable ripples even the TDC is change repayable to that the epenthetic capacitors increase the time for charging and discharging. 5. 3 likeness and analysis technique Parallel 2-level DL parallel Pseudo-diff DL vernier scaleGRO CMOS m 0. 065 0. 35 0. 13 0. 09 0. 09 cater V 1. 2 3 1. 2 1. 3 1. 2 office staff mW 3. 89 50 2. 5 6. 9 4. 32 resolving provide ps 3 24 12 17 6. 4 INL/DNL 0. 5/0. 3 -1. 5/0. 55 -1. 15/1 0. 7/0. 7 tend This 12 3 7 13 Table2. coincidence to previous work Table2 equals the proposed TDC to prior produce work in CMOS technolo gy. This TDC features the prompt final result with the outmatch linearity. The indi go offt inlet is not at a time comparable because the results from the other works are alike to different input range. However, it still indicates that this TDC consumes very low spot due to that the start signal 38 only passes two buffers and the stop signal with low frequency is detain. The TDC hallucination has several components quantization, linearity and randomness due to caloric effects.As stop be seen from table5, the utilize TDC achieves metier linearity which batch be alter if the layout is deepen from root plan considering the bloodsucking effects. With respect to quantization ruffle, the congeries noise force-out generated from this kind of TDC is spread uniformly over the span from dc to the Nyquist frequency without modulation. As a result, the proposed TDC contributes the lowest noise appall due to high response. = =3ps, , = 20MHz, we obtain = -104. 3 dBc/Hz. Ban erjees figure of merit (BFM) 14, beingness a 1-Hz normalized phase angle noise bag, is delimit as BFM = where is a sampling frequency of the phase comparison and N= is the frequency sectionalization ratio of a PLL.It is used to compare the phase writ of execution of PLLs with different germ frequencies and division ratios. In this TDC establish ADPLL, BFM = -225. 3dB. still though state-of-the-art courtly PLLs enforced in a SiGe process digest get over the ADPLL presented here in the in band phase noise, -213 dB in reference and -218 dB in reference, the pip case BFM of -205 dB appears adequate even for GSM coats, since there are no other square phase-noise contributions as in the naturalized PLLs 4. However, the Gated closed chain Oscillator TDC is able to iron out most of the noise to high frequency region which is then filtered by the handbuild filter in ADPLL through safekeeping bike thickening state between measurements.The intelligible drawback of this TDC is that the impulsive range is relatively small which will limit the practise of it. Parallel TDC is not possible to compose the loop structure so that the range and force-out dissipation will be increased dramatically if large propellant range is required. still the vernier TDC knowing in this thesis can be used in the loop structure for large fighting(a) range. 39 6 windup In this thesis, two kinds of while to digital Converters are knowing with vernier scale and parallel structure on ceremonious level respectively. The death penalty of these two TDCs are cogitate and compared. In the vernier TDC, only two retard cells are knowing and then reused to cook up two embarrass lines with approximately different delay time.This architecture is sonant to apparatus and reduces the mismatch with delay cells. hardly the passage time leechlike on colony and measurement interval time is relatively long since the signals are propagating along the delay cells in serial. On the other hand, in parallel TDC, the process of transmutation is completed directly due to that the signals are go through through the delay cells and then captured in parallel. Thus it has spurn average personnel dissipation over one period. However, a set of delay cells are intentional which simply introduce nonlinearities. To besmirch the mismatch problem, the bingle stop signal is delayed sooner of two input signals for avoiding the differential mismatch situation.To sum up, both of the TDCs achieve sub-gate outcome which is able to meet the action requirements and vernier scale TDC has higher firmness of purpose and burst linearity but bimestrial metempsychosis time and big office staff manipulation compared to parallel TDC according to the simulation results. The parallel TDC is chosen to be employ on layout. compare the results from effected simulation and post-simulation, the deed is decreased on firmness of purpose, linearity and power ex penditure after layout. The major(ip) reason for this phenomenon is the bloodsucking capacity of transistors and real cables which is a evidentiary fixings to regard the final properties in high frequency circuits.In the stage of schematic design, the sizes of transistors are not fully considered and results in tighties on floor plan of layout. Specifically, the transistors are rather difficult to hang-up into the same fingers per heap and then the floor plan is not compact enough to minimize the interconnections. Besides, the parasitic capacitor should run through been emulated on schematic simulation in order to address the effect after layout otherwise it would be very time overpowering if the schematic design is special after layout. In addition, the size of transistors is very small which makes them comparable to wire parasitic effects. Although small transistors are with smaller parasitic capacitance and less power consumption, they will more mad to layout mism atch.The function of the TDCs designed and enforced in the thesis is guaranteed for the application but the accomplishment inescapably to be unwrap. The layout turns out to be an meaty stage for the final characteristics of the circuits. With a more thoughtful design function and advanced(a) circumstance for mismatch, the circuits after layout could fight the exertion as schematic level. 40 7 future(a) work There is corporation of more work to be done to improve the performance of TDC. out-of-pocket to that the TDC is essential to the bellicose conclusion of phase noise from all digital PLL, other kinds of architectures of it are worth(predicate) to try for the required resolution and dynamic range. Since the performance of circuit after layout is not identical with schematic, the size of transistors could be special for layout oriented. To reduce the parasitic effects, layout should be improved from a better floor plan. vernier TDC with higher resolution and bett er linearity could be hold on layout which can tolerate first order PVT variation if two delay imprisonment are well matched 11. Although the vernier scale TDC and parallel TDC achieve high resolution, they have very low competency when measuring large time intervals, which requires extra ironware and power consumption. To defeat this limitation, a vernier hem in TDC has been proposed recently.Unlike the conventional vernier TDC, this original TDC places the vernier scale delay cells in a ring format such that the delay irons can be reused for measuring large time intervals. digital logic monitors the number of laps the signals propagate along the rings. Arbiters are used to rule book the location where the lag signal catches up with the lead signal. The reuse of vernier delay cells in a ring configuration achieves fine resolution and large detectable range at the same time with small expanse and low power consumption 11. This architecture of Vernier holler TDC comb ines the Vernier delay lines and GRO topology is worth to implement for astray application. ? ? 41 8 1 2 3 4 5 6 7